Frequency divider with delay compensation
US11075639B1 · kind B1 · utility
1Cited by
6References
8Claims
0Family size
Assignee
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Key dates
| Filing date | May 21, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | May 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/356139
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for controlling a frequency range of a self-resonant frequency (SRF) of a high speed divider implemented in current mode logic (CML) D triggers by controlling a field effect transistor (FET) load resistor bias voltage to FETs operating in linear regions in load resistors in the CML D triggers. Tail currents of the CML D triggers are controlled to track inversely to a resistor value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.