Background timing skew error measurement for RF DAC
US11075643B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2020 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Feb 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/109
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.