Three dimensional circuit formation
US11076492B2 · kind B2 · utility
0Cited by
8References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Dec 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0713
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.