Power management integrated circuit (PMIC), memory module and computing system including a PMIC, and method of operating a memory system
US11079784B2 · kind B2 · utility
2Cited by
2References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Feb 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0409
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power management integrated circuit (PMIC) includes a voltage regulator, a monitoring circuit, and a count register. The voltage regulator is configured to generate an output voltage. The monitoring circuit is configured to receive a feedback voltage of the output voltage, and to determine at each of periodic intervals whether the feedback voltage is outside a threshold voltage range. The count register is configured to store a count value indicative of a number of times the feedback voltage is determined by the monitoring circuit to be outside the threshold voltage range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.