Methods and apparatus to perform error detection and/or correction in a memory device
US11080135B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2017 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jun 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31713
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example apparatus to monitor memory includes an error manager to compare a first memory location of a first error in the memory to a plurality of memory locations in an error history log, the plurality of memory locations previously identified in the error history log based on errors detected in the memory locations, ones of the memory locations associated with corresponding counters that track the errors detected in the memory locations, and update a first one of the counters corresponding to the first memory location when a first address of the first memory location matches a second address of one of the memory locations in the error history log. The example apparatus further includes a command generator to transmit a command to an error corrector to perform error correction on the first memory location when the first one of the counters satisfies a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.