Concurrent fault co-simulator
US11080444B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3308
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Devices, methods, computer-readable media, and other embodiments are described for concurrent functional and fault co-simulation of a circuit design. One embodiment involves accessing simulation data for a circuit design made up of a plurality of machine regions. A plurality of faults is selected from the simulation data for co-simulation operations of functional simulation and fault simulation of the circuit design, and functional simulation of the plurality of machine regions is initiated using the simulation data. A first machine region is identified during the functional simulation as associated with at least a first fault of the plurality of faults. A functional simulation of the first machine region is performed, and a divergence point associated with the first fault is identified. A fault simulation for the first fault is performed using the functional simulation of the first machine region and the divergence point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.