Patent · US Active

Automated design closure with abutted hierarchy

US11080456B2 · kind B2 · utility

2Cited by
14References
17Claims
0Family size

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Inventors

Key dates

Filing dateNov 28, 2019
Grant dateAug 3, 2021
Priority date
Expiry dateNov 28, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/398
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.