Patent · US Active

Compression for deep learning in case of sparse values mapped to non-zero value

US11080611B2 · kind B2 · utility

2Cited by

2References

21Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Ajit Singh · Plainsboro, US
Bharat Daga · Fremont, US
Michael Behar · Jerusalem, IL

Key dates

Filing date	Dec 22, 2017
Grant date	Aug 3, 2021
Priority date	—
Expiry date	Oct 26, 2038

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments described herein provide a processing apparatus comprising compute logic to generate neural network data for a convolutional neural network (CNN) and write the neural network data to a memory buffer. The compute logic additionally includes a direct memory access (DMA) controller including a hardware codec having an encode unit and a decode unit, the DMA controller to read the neural network data from the memory buffer, encode the neural network data via the encode unit, write encoded neural network data to a memory device coupled with the processing apparatus, write metadata for the encoded neural network data to the memory device coupled with the processing apparatus, and decode encoded neural network data via the decode unit in response to a request from the compute logic.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.