Via placement for slim border electro-optic display backplanes with decreased capacitive coupling between t-wires and pixel electrodes
US11081066B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Feb 12, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Feb 12, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0219
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An electro-optic display including an array of pixel electrodes, where each row of pixel electrodes is associated with a source line, and that source line is connected to a drive chip with a T-wire that connects from the back of the substrate to the front of the substrate through a via. The vias are spaced out, such as in a zig-zag pattern or a pseudo-random pattern to reduce the capacitive coupling between the T-wires when adjacent pixels are driven, for example when presenting text characters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.