Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask
US11081387B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2019 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jan 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.