Bias circuitry and biasing method
US11082045B2 · kind B2 · utility
0Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jun 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bias circuitry includes a simulation circuit and a level shifter circuit. The simulation circuit is configured to simulate circuit architecture of a processing circuitry, in which the processing circuitry is biased by a bias signal, in order to generate output signals according to input signals. The level shifter circuit is configured to increase a voltage difference between a first node and a second node of the simulation circuit, in which the first node is for tracking an output common mode voltage of the output signals, and the second node is for outputting the bias signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.