Semiconductor integrated circuit, receiving device, and control method of receiving device
US11082048B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Sep 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, in a semiconductor integrated circuit, a determination circuit is configured to generate first transition information, second transition information and phase determination information, with respect to a signal level of a modulation signal. The first transition information indicates a state of a first transition edge of transition between a first signal level and a second signal level. The second transition information indicates a state of a second transition edge of transition between a third signal level and a fourth signal level. The phase determination information indicates a result of a phase determination of a clock signal. An estimation circuit is configured to estimate a deviation between a timing of the first transition edge and a timing of the second transition edge according to the first transition information, the second transition information, and the phase determination information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.