Decoding scheme for error correction code structure in data storage devices
US11082069B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Apr 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6502
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining features for each of a plurality of component codes corresponding to the data by decoding each of the plurality of component codes, determining an extrinsic value output for each of the component codes based on the features, and after the extrinsic value output for each of the component codes is determined, decoding each of the plurality of component codes based on the extrinsic value outputs of all other component codes of the component codes. Each of the component codes depends on all other component codes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.