Clock data recovery apparatus and method
US11082200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0338
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery apparatus is provided that includes a sampling circuit, a storage circuit and a determining circuit. The sampling circuit includes sampling units each sampling a received data according to one of reference clock signals to generate a sampling result. The storage circuit includes FIFO storage units configured to store the sampling result of the received data corresponding to different time spots. The determining circuit is configured to set a certain number of received data as a reference data pattern, to adjust a starting position of a sampling window according to a transition point of sampled values within the reference data pattern when only one data transition exists therein and adjust a length of the sampling window according to an amount of high state sample points of the sampled values within the reference data pattern when more than one data transitions exist therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.