Multi-tap hybrid equalization scheme for 24GBPS GDDR6 memory interface transmitter
US11082267B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03528
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The embodiments described herein provide for a method and system for implementing a multi-tap hybrid-equalization technique devoid of ISI jitter and PSI jitter in the high-speed data path to achieve 24 Gbps operating speed in systems utilizing GDDR6 DRAM. The method includes receiving an original data signal at a first TFFE circuit and receiving an altered data signal at a second TFFE circuit. The method further comprises generating a time-domain-equalized original data signal using a set of TFFE coefficients from the original data signal. The method further comprises generating a time-domain-equalized altered data signal using the set of TFFE coefficients from the altered data signal. The method further comprises generating, a time-and-voltage-domain-equalized data signal from the time-domain-equalized original data signal and the time-domain-equalized altered data signal at a voltage-feed forward equalization (VFFE) circuit using a set of VFFE coefficients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.