Instruction length decoder system and method
US11086627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Oct 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/544
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is provided that includes an instruction buffer that stores bytes representative of one or more macroinstructions and instruction length decoder circuitry. The instruction length decoder circuitry includes a non-sequential first multiplexer circuitry having first input lines receiving a first input data representative of a speculative length of a first macroinstruction of the macroinstructions, and first selector that selects from the first input lines via a one-hot selector vector. The instruction length decoder circuitry also includes a first output line communicatively coupled to second selector, wherein the first output line causes the selector to select from a second input data representative of a first location of a first ending byte for the first macroinstruction with respect to a value x. The first multiplexer circuitry and the second selector may output start and end byte locations for the macroinstructions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.