Finish exception handling of an instruction completion table
US11086630B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 27, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/481
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a dispatch stage configured to dispatch a plurality of instructions in a program order, and an issue stage configured to issue at least one instruction among the plurality of instructions. The computer system further includes an execution stage configured to execute the at least one instruction to generate a finish report and to determine the at least one instruction is one of an exception-free instruction or an exception instruction. In response to determining the exception-free instruction, a first finish report associated with the exception-free instruction is output to a completion stage. In response to determining the exception instruction, a second finish report associated with the exception instruction is output to an exception unit so as to halt output of the second finish report to the completion stage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.