System comprising non-volatile memory device and one or more persistent memory devices in respective fault domains
US11086739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 29, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system includes a host processor, a volatile memory device coupled to the host processor, and at least a first persistent memory device coupled to the host processor. The host processor is configured to execute one or more applications. The volatile memory device and the first persistent memory device are in respective distinct fault domains of the system, and at least one of a plurality of data objects generated by a given one of the applications is accessible from multiple distinct storage locations in respective ones of the distinct fault domains. For example, the host processor and the volatile memory device may be in a first one of the distinct fault domains and the first persistent memory device may be in a second one of the distinct fault domains. The data object remains accessible in one of the fault domains responsive to a failure in another of the fault domains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.