Identifying false positives in test case failures using combinatorics
US11086768B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Feb 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3698
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for detecting and localizing a fault in a system under test (SUT) includes generating an initial set of test cases using combinatorics test design. The method further includes determining, based at least in part on a first set of execution results, a set of failing test cases. The method further includes determining, based on a machine learning model, a subset of false positives from the failing test cases. The method further includes generating a set of new test cases from a selected failing test case that is not in the subset of false positives. The method further includes executing the set of new test cases to obtain a second set of execution results, and localizing the fault based at least in part on the second set of execution results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.