Single transistor multiplier and method therefor
US11087099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Nov 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45632
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multiplier has a MOSFET in a common source configuration. A MOSFET current source is coupled to a drain terminal of the MOSFET. An inverter has an input coupled to the drain terminal of the MOSFET. An output of the inverter gates two currents whose current magnitudes are proportional. A first capacitor has a first terminal coupled to a first of the two currents and a gate of the MOSFET and a second terminal grounded. A second capacitor has a first terminal coupled to a second of the two currents and a second terminal coupled to the first of the two currents. The multiplier is first reset by discharging a gate capacitance of the MOSFET and then allowing it to be recharged to a Vt comparator threshold after which a charge is removed from the gate terminal of the MOSFET reducing a voltage on the gate terminal below the Vt comparator threshold, causing the two currents to be enabled until the Vt comparator threshold reaches a previous Vt comparator threshold and the inverter turns off the two currents. In a next reset phase, the second capacitor holds a multiplied value of charge.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.