Manufacturing method of TFT array substrate
US11087985B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 11, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Jan 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/423
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a manufacturing method of the TFT array substrate. Compared to existing 4M process, the invention changes the structural design of the semi-transmissive mask for the photoresist layer for patterning the source/drain metal layer and the semiconductor layer. The edge forms a reduced thickness edge portion, so that the edge of the photoresist layer is thinned, and thereby the width of the photoresist layer is easily reduced in subsequent processes, and the semiconductor layer at the edge of the metal wire structure is easily etched during dry etching, reducing the tailing problem of the active layer at edges of source/drain to achieve finer metal wire structure, and improve optical stability, electrical performance, aperture ratio, reliability, power consumption, and the overall performance of the TFT array substrate. The residual problem of amorphous and heavily doped silicon on source/drain edge in original process is solved or reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.