Transistor outline housing with high return loss
US11088096B2 · kind B2 · utility
0Cited by
2References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Oct 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30111
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A transistor outline housing is provided that includes a header for an optoelectronic component. The header has electrical feedthroughs in the form of connection pins embedded in a potting compound. The header has a recess in which at least one of the connection pins in one of the feedthroughs extends out of the lower surface of the header.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.