Semiconductor device for enhancing electrostatic discharge protection and layout structure thereof
US11088132B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Aug 29, 2017 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device for enhancing electrostatic discharge (ESD) protection and a layout structure thereof are provided. An ESD protection device and a protected device (300) with a small feature linewidth are located on the same well region. The device (300) with the small feature linewidth is located at a middle portion. The ESD protection device is disposed at both sides of the device (300) with the small feature linewidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.