Gate structure of semiconductor device and manufacturing method therefor
US11088253B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 2018 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Oct 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/658
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate structure of a semiconductor device, includes: a trench gate and a planar gate including a plurality of polysilicon structures (406) separated from each other; the gate structure of the semiconductor device further includes a well region (503) being adjacent to the trench gate and being disposed under the planar gate; a first conduction type doped region (504) being disposed in the well region (503) and including a plurality of regions separated from each other, wherein each region is disposed under adjacent polysilicon structures (406), and respective regions are electrically connected to the planar gate; and a source (504a) being disposed in the well region (503); wherein the trench gate includes: a silicon oxide filler (202) including a side wall silicon oxide and a bottom silicon oxide; a control gate (402) being located over the trench gate, wherein a side wall of the control gate is enclosed by the side wall silicon oxide, and the control gate (402) is electrically-connected to the planar gate; a shield gate (404) having a single segment structure or a longitudinally arranged multiple segments structure; and an insulation silicon oxide (204) being filled between adjace…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.