Method and apparatus for eliminating crosstalk effects in high switching-speed power modules
US11088680B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 16, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Jul 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/687
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for reducing Miller effect in SiC MOSFETs are provided. An example apparatus includes a plurality of SiC MOSFETs and a Miller current cancellation circuit configured to mitigate Miller current induced by switching transients associated with the plurality of SiC MOSFETS. The Miller current cancellation circuit includes a two-stage voltage sampling circuit configured to sample a drain to source voltage of a SiC MOSFET of the plurality of SiC MOSFETs, a voltage inverting circuit configured to invert the sampled drain to source voltage, and an injection capacitor configured to generate, by way of receiving the inverted sampled drain to source voltage as input, inverse Miller current to mitigate the Miller current within the plurality of SiC MOSFETS.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.