Memory controllers and memory systems including the same
US11088710B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
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Key dates
| Filing date | Mar 5, 2020 |
| Grant date | Aug 10, 2021 |
| Priority date | — |
| Expiry date | Mar 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/118
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory controller configured to control a memory module, the memory controller including processing circuitry configured to perform ECC decoding on a read codeword from the memory module using a first portion of a parity check matrix to generate a first syndrome and a second syndrome, determine a type of error in the read codeword based on the second syndrome and a decision syndrome, the decision syndrome corresponding to a sum of the first syndrome and the second syndrome, and output a decoding status flag indicating the type of error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.