Start-up speed enhancement circuit and method for lower-power regulators
US11092988B2 · kind B2 · utility
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6References
19Claims
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Key dates
| Filing date | Sep 23, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Sep 24, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/468
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A start-up speed enhancement circuit and method for lower-power regulators is provided herein. Operations of a method can comprise detecting a condition of a power regulator being a start-up condition and applying a first current and a second current to the power regulator based on the start-up condition. The method can also comprise determining the condition of the power regulator changes from the start-up condition to an operation condition. Further, the method can comprise stopping application of the second current to the power regulator based on the condition being the operation condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.