FP16-S7E8 mixed precision for deep learning and other algorithms
US11093579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to mixed-precision vector multiply-accumulate (MPVMAC) In one example, a processor includes fetch circuitry to fetch a compress instruction having fields to specify locations of a source vector having N single-precision formatted elements, and a compressed vector having N neural half-precision (NHP) formatted elements, decode circuitry to decode the fetched compress instruction, execution circuitry to respond to the decoded compress instruction by: converting each element of the source vector into the NHP format and writing each converted element to a corresponding compressed vector element, wherein the processor is further to fetch, decode, and execute a MPVMAC instruction to multiply corresponding NHP-formatted elements using a 16-bit multiplier, and accumulate each of the products with previous contents of a corresponding destination using a 32-bit accumulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.