Language and compiler that generate synchronous digital circuits that maintain thread execution order
US11093682B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 14, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Jan 14, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded programming language and compiler generates synchronous digital circuits that maintain thread execution order by generating pipelines with code paths that have the same number of stages. The compiler balances related code paths within a pipeline by adding additional stages to a code path that has fewer stages. Programming constructs that, by design, allow thread execution to be re-ordered, may be placed in a reorder block construct that releases threads in the order they entered the programming construct. First-in-first-out (FIFO) queues pass local variables between pipelines. Local variables are popped from FIFOs in the order they were pushed, preserving thread execution order across pipelines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.