Efficient parallel computing method for box filter
US11094071B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T5/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient parallel computing method for a box filter, includes: step 1, with respect to a given degree of parallelism N and a radius r of the filter kernel, establishing a first architecture provided without an extra register and a second architecture provided with the extra register; step 2, building a first adder tree for the first architecture and a second adder tree for the second architecture, respectively; step 3, searching the first adder tree and the second adder tree from top to bottom, calculating the pixel average corresponding to each filter kernel by using the first adder tree and the second adder tree, respectively, and counting resources required to be consumed by the first architecture and the second architecture, respectively; and, step 4, selecting one architecture consuming a relatively small resources from the first architecture and the second architecture for computing the box filter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.