Memory chip or memory array for wide-voltage range in-memory computing using bitline technology
US11094355B1 · kind B1 · utility
3Cited by
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24Claims
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Key dates
| Filing date | May 5, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | May 5, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.