Vertical transistor device with source/drain regions comprising a twi-dimensional (2D) material and methods of making such vertical transistor devices

US11094791B1 · kind B1 · utility

Assignee

• GLOBALFOUNDRIES U.S. Inc. · US

Inventors

• Heng Yang · Fishkill, US
• David Pritchard · Beacon, US
• Kai Sun · Beijing, CN
• Hongru Ren · Mechanicville, US
• Neha Nayyar · Clifton Park, US
• Manjunatha Prabhu · Malta, US
• Elizabeth Strehlow · Malta, US
• Salvatore Cimino · Cohoes, US

Key dates

• Filing date: Jan 30, 2020
• Grant date: Aug 17, 2021
• Expiry date: Jan 30, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/882

Abstract

One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.