Amplification interface, and corresponding measurement system and method for calibrating an amplification interface
US11095261B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Feb 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45514
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.