Hybrid architectures for check node processing of extended min-sum (EMS) decoding of non-binary LDPC codes
US11095308B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1171
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.