Small loop delay clock and data recovery block for high-speed next generation C-PHY
US11095425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Aug 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4917
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for communication over a multi-wire, multi-phase interface are disclosed. A clock recovery method includes generating a combination signal that includes transition pulses, each transition pulse being generated responsive to a transition in a difference signal representative of a difference in signaling state of a pair of wires in a three-wire bus. The combination signal is provided to a logic circuit that is configured to provide a clock signal as its output, where pulses in the combination signal cause the clock signal to be driven to a first state. The logic circuit receives a reset signal that is derived from the clock signal by delaying transitions to the first state while passing transitions from the first state without added delay. The clock signal is driven from the first state after passing a transition of the clock signal to the first state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.