Method and apparatus for mitigating performance degradation in digital low-dropout voltage regulators (DLDOs) caused by limit cycle oscillation (LCO) and other factors
US11099591B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Sep 17, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG05F1/614
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.