Multi-bank memory with one read port and one or more write ports per cycle
US11099746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2016 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Dec 8, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.