Storage array with dynamic cache memory configuration provisioning based on prediction of input-output operations
US11099754B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | May 14, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises at least one processing device comprising a processor coupled to a memory. The at least one processing device is configured to receive, via a multi-path layer of at least one host device, at least one indication of a predicted distribution of input-output operations directed from the at least one host device to a storage system for a given time interval. The at least one processing device is also configured to determine a cache memory configuration for a cache memory associated with the storage system based at least in part on the at least one indication of the predicted distribution of input-output operations for the given time interval. The at least one processing device is further configured to provision the cache memory with the determined cache memory configuration for the given time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.