Gate driving sub-circuit, driving method and gate driving circuit
US11100834B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 12, 2018 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/028
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driving sub-circuit, a driving method and a gate driving circuit are provided. The gate driving sub-circuit includes an input signal end, a shift signal output end, an inverted phase shift signal output end, a positive phase shift clock signal input end, an inverted phase shift clock signal input end, a first control clock signal input end, a second control clock signal input end, a first gate driving signal output end, a second gate driving signal output end, a shift register circuit and a control output circuit. The control output circuit includes a first control output sub-circuit and a second control output sub-circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.