Display device
US11100882B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Dec 28, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/0223
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a display device that adopts an SSD scheme, a demultiplexer circuit has provided for each source bus line, a compensating transistor whose first conduction terminal is connected to the source bus line and whose second conducting terminal is maintained in a floating state. In such a configuration, for example, at the same timing as a connection control transistor changes from an on state to an off state due to a change from a high level to a low level of a control signal that is supplied to a control terminal of the connection control transistor, a control signal that is supplied to a control terminal of the compensating transistor changes from the low level to the high level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.