Semiconductor memory device
US11100958B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Jul 26, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprising a substrate including a cell region, first and second contact regions, and a bit peripheral circuit region disposed between the first and second contact regions. A first stack structure is disposed on the cell region and the first contact region. A second stack structure is disposed on the cell region and the second contact region. A peripheral transistor is disposed on the bit peripheral circuit region and is electrically connected to the first and second stack structures. Each of the first and second stack structures comprises semiconductor patterns vertically stacked on the cell region, and conductive lines having connection with the semiconductor patterns and extending along a first direction from the cell region onto corresponding first and second contact regions. The conductive lines have stepwise structures on the first and second contact regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.