Data first-in first-out (FIFO) circuit
US11100963B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data first-in first-out (FIFO) circuit includes a register unit, a plurality of data multiplexers, and an output multiplexer. The register unit includes a plurality of decoders and a plurality of N registers. The decoders are used for outputting a plurality of decoded signals in response to a plurality of corresponding input control signals and at least one input enabling signal. The N registers are configured to receive input data in response to the corresponding decoded signals from the corresponding decoders. The data multiplexers each are coupled to M ones of the registers, wherein N and M are positive integers, N is equal to or greater than four, M is equal to or greater than two, and N is greater than M. The output multiplexer, coupled to the data multiplexers, is used for providing a corresponding output from the data multiplexers sequentially.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.