Low-power SRAM memory cell and application structure thereof
US11100979B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-power SRAM memory cell includes five word lines and four bit lines. The five word lines are a first word line, a second word line, a third word line, a fourth word line and a fifth word line. The four bit lines are a first bit line, a second bit line, a third bit line, and a fourth bit line. During the operation process of calculating a binary 10×11, the first word line is 1, the second word line is 0, the third word line is 0, the fourth word line is 1, the high bit stored in the bit cell is 1, and the low bit is 1. The voltage value of the fifth word line is 0.73 volt. At this time, the first bit line, the second bit line, and the third bit line do not discharge, while the fourth bit line discharges.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.