Semiconductor package
US11101243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Nov 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15159
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package including a circuit substrate including a plurality of interconnections; a first chip on the circuit substrate; a second chip stacked on the first chip; a plurality of first pads on the circuit substrate, the plurality of first pads overlapping the first chip; a plurality of bumps between the circuit substrate and the first chip; a plurality of second pads on an edge portion of a first side of the circuit substrate, the plurality of second pads electrically connected to the second chip through a conductive wire; an underfill that fills a space between the circuit substrate and the first chip; and a first dam on the circuit substrate, the first dam overlapping the first chip. The first dam includes a conductive material and overlaps at least one of the plurality of interconnections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.