Transistors employing non-selective deposition of source/drain material

US11101268B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Karthik Jambunathan · Hillsboro, US
• Scott Maddox · Hillsboro, US
• Ritesh Jhaveri · Portland, US
• Pratik A. Patel · Berkeley, US
• Szuya S. Liao · Portland, US
• Anand S. Murthy · Beaverton, US
• Tahir Ghani · Portland, US

Key dates

• Filing date: Mar 30, 2017
• Grant date: Aug 24, 2021
• Expiry date: Jun 25, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.