Process for manufacturing NOR memory cell with vertical floating gate
US11101277B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Mar 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrically erasable programmable nonvolatile memory cell includes a semiconductor substrate having a first substrate region and a trench region apart from the first substrate region in a lateral direction, a channel region between the first substrate region and the bottom portion of the trench region, an electrically conductive control gate insulated from and disposed over the first channel portion, an electrically conductive floating gate insulated from the bottom and sidewall portions of the trench region, an insulation region disposed over the second channel portion between the control gate and the second floating gate portion, an electrically conductive source line insulated from the floating gate and electrically connected to the trench region of the substrate, and an electrically conductive erase gate insulated from and disposed over a tip of the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.