Semiconductor memory device
US11101283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
Abstract
A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.