Time-interleaved successive approximation register analog to digital converter with grouped digital to analog capacitors
US11101814B2 · kind B2 · utility
0Cited by
3References
10Claims
0Family size
Inventors
Key dates
| Filing date | Sep 23, 2020 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Sep 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention is a system and method for providing a modified Digital-to-Analog converter (DAC) for use in a time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC), the DAC including grouping of capacitance electrodes by Bit in a DAC, thereby reducing parasitic capacitances, and substantially improving power efficiency and speed to operate at GHz frequencies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.