Electrically testing cleanliness of a panel having an electronic assembly
US11102921B2 · kind B2 · utility
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3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 19, 2019 |
| Grant date | Aug 24, 2021 |
| Priority date | — |
| Expiry date | Feb 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2818
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of assessing a cleanliness of an assembly in a panel during a manufacturing process is provided, wherein an electrical signal of at least one of a predetermined voltage, current or frequency is applied across a first subset and a second subset of nonconnected electrical contacts in a test coupon associated with the assembly, such that the first subset and the second subset have different pitches. In one configuration, the test coupon is tested at higher voltages, currents or frequencies to a point of failure or above a predetermined threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.