Dynamic processor core frequency adjustment
US11106267B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Nov 27, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for managing clock frequency in a multi-core integrated circuit includes determining a minimum allowable operating clock frequency and a maximum allowable operating clock frequency for an integrated circuit having a plurality of processor cores. A plurality of clock sources is configured to provide a corresponding plurality of clock frequencies between the minimum allowable operating clock frequency and the maximum allowable operating clock frequency. A total number of active processor cores is determined. If it is determined that all of the plurality the processor cores are active, all active processor cores are operated at the minimum allowable operating clock frequency. If it is determined that the total number of active processor cores is lower than a threshold number, the clock frequency of one or more active processor cores is increased based on available electrical current budget.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.